library ieee ;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity VGA_clock is
generic(pixels_per_sec: natural:=800); 
port(	
	clock:		in std_logic;
	sw: in std_logic_vector(3 downto 0);
	pulse: 		out std_logic
);
end VGA_clock;

----------------------------------------------------

architecture behv of VGA_clock is

	signal terminal_count : natural := 400000;
	
	signal count : natural range 0 to 400000 := 0;

begin
process(sw)
	begin
		if sw(0) = '1' then
			terminal_count <= 400000;
		elsif sw(1) = '1' then
			terminal_count <= 114285;
		elsif sw(2) = '1' then
			terminal_count <= 80000;
		elsif sw(3) = '1' then
			terminal_count <= 40000;
		else 
			terminal_count <= 400000;
		end if;
end process;

	process(clock)
	--variable clk_cnt: integer range 0 to 49999999:=1;
	begin
		if rising_edge(clock) then
			if count = terminal_count then
				count <= 0;
			else
				count <= count + 1;
			end if;
		end if;
	end process;
	
	pulse <= '1' when count = terminal_count else '0';

end behv;


